Implementations

Please read the Grøstl Implementation Guide before implementing Grøstl yourself.

The reference implementation, some optimized code in C and assembly language are part of the new NIST submission package for tweaked Grøstl.

These and other software implementations have also been submitted to the eBASH benchmarking project. This tarball contains the Grøstl implementations currently (or soon to be) included in eBASH. Among these are

Software benchmarks of Grøstl from eBASH

All eBASH benchmarking results for Grøstl-256 can be found here, all results for Grøstl-512 can be found here.

Digest sizeProcessorModeSpeed
224/256 Intel Core i7-2600K (with AES-NI) 64-bit 9.6 cycles/byte
Intel Xeon E5620 (with AES-NI) 64-bit 11.3 cycles/byte
AMD Phenom II X6 64-bit 17.3 cycles/byte
AMD Opteron 8354 64-bit 19.8 cycles/byte
Intel Core 2 Duo E6400 64-bit 22.3 cycles/byte
Intel Pentium M 32-bit 38.8 cycles/byte
384/512 Intel Core i7-2600K (with AES-NI) 64-bit 13.8 cycles/byte
Intel Xeon E5620 (with AES-NI) 64-bit 16.2 cycles/byte
AMD Phenom II X6 64-bit 31.7 cycles/byte
AMD Opteron 8354 64-bit 33.6 cycles/byte
Intel Core 2 Duo E8400 64-bit 32.2 cycles/byte
Intel Pentium M 32-bit 76.1 cycles/byte

8-bit software implementations of Grøstl

Johannes Feichtner has implemented new 8-bit versions of Grøstl-256 for an 8-bit ATmega163 microcontroller, based on the work by Günther A. Roland. This results in by far the smallest RAM implementation (136 bytes) of any SHA-3 finalist. The detailed results are given below.

Version (state)RAM (bytes)ROM (bytes)Speed for 1536 (cycles/byte)
Low RAM1361898571
Low ROM5191322498
High speed5334982458

Hardware ASIC implementations of Grøstl-0

Stefan Tillich developed high-speed Grøstl-0-256 ASIC implementations in 0.18µm technology of UMC. Here are the synthesis results.

Total area (mm²)Total area (GE)Throughput (Gbit/s)
547,227.4758,4036.290
538,462.4157,4676.141
523,472.7455,8675.690
471,626.0650,3342.725